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ENGR3520HomeworkChapter12

Multiple Choice
Identify the choice that best completes the statement or answers the question.
 

 1. 
The flip-flop is the basic circuit used in
a.
combinational logic circuits.
c.
sequential logic circuits.
b.
arithmetic circuits.
d.
all of the above
 

 2. 
When a circuit design uses only gates and no flip-flops it is called
a.
sequential logic.
c.
gated logic.
b.
SOP logic.
d.
combinational logic.
 

 3. 
Combinational logic describes a circuit that contains no
a.
AND gates.
c.
NAND gates.
b.
inverters.
d.
flip-flops.
 

 4. 
What is the modulus of a counter which counts from 0 to 6 and then recycles back to 0?
a.
MOD-5
c.
MOD-7
b.
MOD-6
d.
MOD-8
 

 5. 
What is the modulus of a counter which counts from 0 to 4 and then recycles back to 0?
a.
MOD-5
c.
MOD-7
b.
MOD-6
d.
MOD-8
 

 6. 
What is the modulus of a counter which counts from 0 to 7 and then recycles back to 0?
a.
MOD-5
c.
MOD-7
b.
MOD-6
d.
MOD-8
 

 7. 
How many flip-flops are required to make a counter which counts from 0 to 7?
a.
2
c.
4
b.
3
d.
5
 

 8. 
How many flip-flops are required to make a counter which counts from 0 to 3?
a.
2
c.
4
b.
3
d.
5
 

 9. 
How many flip-flops are required to make a counter which counts from 0 to 15?
a.
2
c.
4
b.
3
d.
5
 

 10. 
How many flip-flops are required to make a counter which counts from 0 to 5?
a.
2
c.
4
b.
3
d.
5
 

 11. 
How many flip-flops are required to make a counter which counts from 0 to 31?
a.
6
c.
5
b.
3
d.
4
 

 12. 
What must be connected to the J and K inputs of each flip-flop in order to construct an asynchronous MOD-8 counter?
a.
J and K are both connected HIGH.
c.
J is connected HIGH, K is connected LOW.
b.
J is connected LOW, K is connected HIGH.
d.
J and K are both connected LOW.
 

 13. 
A three-bit binary down-counter counts from
a.
8 to 1.
c.
7 to 0.
b.
0 to 7.
d.
8 to 0.
 

 14. 
Which type of counter is constructed if the clock of each flip-flop connects to Q while the output comes from mc014-1.jpg?
a.
a down-counter
c.
an asynchronous counter
b.
a synchronous counter
d.
an up-counter
 

 15. 
A pulse of short duration which is used to reset a counter once it reaches a specific count is a
a.
trigger.
c.
clock.
b.
glitch.
d.
preset.
 

 16. 
What design consideration distinguishes synchronous counters from asynchronous counters?
a.
Synchronous counters have less delay.
c.
Synchronous counters are CMOS.
b.
Synchronous counters are slower.
d.
Synchronous counters can count higher.
 

 17. 
Which design characteristic distinguishes synchronous counters from asynchronous counters?
a.
Synchronous counters do not use J-K flip-flops.
b.
A common clock is tied to the clock input of all flip-flops in a synchronous counter.
c.
The J and K inputs of each flip-flop in a synchronous counter are tied HIGH.
d.
Synchronous counters never use the TOGGLE mode.
 

 18. 
What is the mode of the flip-flops in an asynchronous counter?
a.
set
c.
hold
b.
toggle
d.
The mode changes.
 

 19. 
When flip-flops are connected with one output to the next input, they are in what type of configuration?
a.
ripple
c.
stair step
b.
cascade
d.
totem pole
 

 20. 
A state diagram is
a.
a truth table.
b.
a map.
c.
a diagram showing different inputs and outputs.
d.
the same as a schematic.
 

 21. 
When all flip-flop inputs are driven by the same clock signal, the counter is known as a
a.
Johnson counter.
c.
synchronous counter.
b.
asynchronous counter.
d.
ripple counter.
 

 22. 
What is the maximum value possible out of a binary counter that has five flip-flops?
a.
32
c.
25
b.
5
d.
16
 

 23. 
A five-bit binary up-counter counts from
a.
0 to 5.
c.
0 to 31.
b.
0 to 25.
d.
5 to 0.
 



 
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