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ENGR3520HomeworkChapter10

Multiple Choice
Identify the choice that best completes the statement or answers the question.
 

 1. 
The data storage device which can be constructed using two NAND gates or two NOR gates is the
a.
encoder.
c.
S-R flip-flop.
b.
J-K flip-flop.
d.
multiplexer.
 

 2. 
The input combination that drives the output of a NOR gate S-R flip flop to Q = 1 and mc002-1.jpg = 0 is ________.
a.
S = 1, R = 1
c.
S = 1, R = 0
b.
S = 0, R = 0
d.
S = 0, R = 1
 

 3. 
The input combination that drives the output of a NOR gate S-R flip-flop to Q = 0 and mc003-1.jpg = 1 is ________.
a.
S = 0, R = 1
c.
S = 1, R = 1
b.
S = 1, R = 0
d.
S = 0, R = 0
 

 4. 
The input combination that drives the output of a NOR gate S-R flip-flop to Q = 0 and mc004-1.jpg = 0 is ________.
a.
S = 1, R = 1
c.
S = 0, R = 1
b.
S = 0, R = 0
d.
S = 1, R = 0
 

 5. 
When a flip-flop is SET, ________.
a.
Q and mc005-1.jpg = 1
c.
Q = 0
b.
mc005-2.jpg = 1
d.
Q = 1, mc005-3.jpg = 0
 

 6. 
When a flip-flop is RESET, ________.
a.
Q = 1, mc006-1.jpg = 0
c.
Q = 0, mc006-3.jpg = 0
b.
Q = 0, mc006-2.jpg = 1
d.
Q = mc006-4.jpg
 

 7. 
The waveforms below represent the inputs to a S-R flip-flop. During which time interval(s) will the Q output of the flip-flop be LOW?

mc007-1.jpg
a.
1
c.
2 and 3
b.
2
d.
4
 

 8. 
The waveforms below represent the inputs to a S-R flip-flop. During which time interval(s) will the Q output of the flip-flop be HIGH?

mc008-1.jpg
a.
1
c.
4
b.
1 and 2
d.
3 and 4
 

 9. 
A gated S-R flip-flop can be constructed from two AND gates and two NOR gates or from
a.
four AND gates.
c.
four OR gates.
b.
four NOR gates.
d.
four NAND gates.
 

 10. 
A gated S-R flip-flop goes into the SET condition when
a.
S is LOW
R is HIGH
Enable is LOW
b.
S is HIGH
R is HIGH
Enable is HIGH
c.
S is HIGH
R is LOW
Enable is HIGH
d.
S is HIGH
R is LOW
Enable is LOW
 

 11. 
The waveforms below represent the inputs to a gated S-R flip-flop. During which time interval(s) will the Q output of the flip-flop be HIGH?

mc011-1.jpg
a.
2
c.
1
b.
3
d.
3 and 4
 

 12. 
The waveforms below represent the inputs to a gated S-R flip-flop. During which time interval(s) will the Q output of the flip-flop be HIGH?

mc012-1.jpg
a.
1
c.
3 and 4
b.
3
d.
It will not be HIGH.
 

 13. 
Which flip-flop has no invalid or unused state?
a.
gated S-R flip-flop
c.
D latch
b.
S-R flip-flop
d.
NAND flip-flop
 

 14. 
The waveforms below represent the inputs to a D latch. During which time interval(s) will its Q output be HIGH?

mc014-1.jpg
a.
4 and 5
c.
4
b.
3 and 4
d.
1 and 2
 

 15. 
The waveforms below represent the inputs to a D latch. During which time interval(s) will its Q output be HIGH?

mc015-1.jpg
a.
3, 4, and 5
c.
3 and 4
b.
1
d.
It will not be HIGH.
 

 16. 
An edge-triggered flip-flop can only change states when
a.
the D input is HIGH.
c.
the trigger input changes levels.
b.
the trigger is HIGH.
d.
the trigger is LOW.
 

 17. 
Which of the following flip-flops have synchronous inputs?
a.
7474 D-flip-flop
c.
S-R flip-flop
b.
NAND flip-flop
d.
all of the above
 

 18. 
An input which can only be accepted when an enable or trigger is present is called
a.
RESET.
c.
asynchronous.
b.
synchronous.
d.
data.
 

 19. 
The inputs on a 7474 D flip-flop are S, R, D and clock. Which of these are asynchronous?
a.
S and R
c.
only S
b.
only D
d.
all of the above
 

 20. 
A master-slave flip-flop is
a.
asynchronous.
c.
edge-triggered.
b.
level-triggered.
d.
a new design.
 

 21. 
The logic states of a J-K flip-flop are SET, RESET, HOLD, and
a.
ENABLE.
c.
TOGGLE.
b.
TRIGGER.
d.
CLEAR.
 

 22. 
TOGGLE state of a J-K flip-flop means that the Q and mc022-1.jpg outputs will
a.
switch to Q = 1 and mc022-2.jpg = 0.
c.
switch to zero.
b.
switch to their opposite state.
d.
become the same as J and K.
 

 23. 
If the inputs of a J-K flip-flop are J = 1 and K = 1 while the outputs are Q = 0 and mc023-1.jpg = 1, what will the outputs be after the next clock pulse occurs?
a.
Q = 1, mc023-2.jpg = 0
c.
Q = 1, mc023-4.jpg = 1
b.
Q = 0, mc023-3.jpg = 0
d.
Q = 0, mc023-5.jpg = 1
 

 24. 
If the inputs of a J-K flip-flop are J = 0 and K = 0 while the outputs are Q = 0 and mc024-1.jpg = 1, what will the outputs be after the next clock pulse occurs?
a.
Q = 0, mc024-2.jpg = 1
c.
Q = 0, mc024-4.jpg = 0
b.
Q = 1, mc024-3.jpg = 1
d.
Q = 1, mc024-5.jpg = 0
 

 25. 
If the inputs of a J-K flip-flop are J = 1 and K = 0 while the outputs are Q = 0 and mc025-1.jpg = 1, what will the outputs be after the next clock pulse occurs?
a.
Q = 0, mc025-2.jpg = 1
c.
Q = 0, mc025-4.jpg = 0
b.
Q = 1, mc025-3.jpg = 1
d.
Q = 1, mc025-5.jpg = 0
 

 26. 
The symbol used on logic diagrams for an edge-triggered clock input is
a.
a small circle.
c.
a small triangle.
b.
a small arrow.
d.
mc026-1.jpg
 

 27. 
A negative edge-triggered flip-flop will only accept inputs when the clock
a.
is HIGH.
c.
changes from LOW to HIGH.
b.
is LOW.
d.
changes from HIGH to LOW.
 

 28. 
A positive edge-triggered flip-flop will only accept inputs when the clock
a.
is HIGH.
c.
is LOW.
b.
changes from LOW to HIGH.
d.
changes from HIGH to LOW.
 

 29. 
The waveforms below represent the inputs to a negative edge-triggered J-K flip-flop. At which point(s) will its Q output go HIGH?

mc029-1.jpg
a.
point 1
c.
point 3
b.
point 2
d.
points 3 and 4
 

 30. 
The waveforms below represent the inputs to an negative edge-triggered J-K flip-flop. At which point(s) will its Q output go HIGH?

mc030-1.jpg
a.
point 3
c.
points 3 and 4
b.
point 4
d.
point 2
 

 31. 
What will happen to the output from a negative edge-triggered J-K flip-flop at point 2 of this timing diagram?

mc031-1.jpg
a.
It will HOLD.
c.
It will RESET.
b.
It will SET.
d.
It will TOGGLE.
 

 32. 
What will happen to the output from a negative edge-triggered J-K flip-flop at point 1 of this timing diagram?

mc032-1.jpg
a.
It will TOGGLE.
c.
It will SET.
b.
It will RESET.
d.
It will HOLD.
 

 33. 
If data is brought into the J terminal and its complement to the K terminal, a J-K flip-flop operates as a(n)
a.
gated S-R flip-flop.
c.
S-R flip-flop.
b.
D flip-flop.
d.
TOGGLE flip-flop.
 

 34. 
A flip-flop is in the SET condition when ________.
a.
Q = 0, mc034-1.jpg = 1
c.
Q = 1, mc034-2.jpg = 0
b.
Q = 0
d.
Q and mc034-3.jpg change to opposite states.
 

 35. 
A flip-flop is in the RESET condition when ________.
a.
Q = 1
c.
Q = 0, mc035-2.jpg = 1
b.
Q and mc035-1.jpg change to opposite states.
d.
Q = 1, mc035-3.jpg = 1
 

 36. 
Inputs which cause the output of a flip-flop to change instantaneously are
a.
edge-triggered.
c.
triggered.
b.
asynchronous.
d.
synchronous.
 

 37. 
Which of the following is not a name used with flip-flops?
a.
gate
c.
memory
b.
register
d.
latch
 

 38. 
Circuits that operate sequentially, in step with a control input are called
a.
asynchronous.
c.
synchronous.
b.
memory.
d.
latching.
 

 39. 
Which type of flip-flop uses only one input to both Set and Reset?
a.
single
c.
toggle
b.
F
d.
D
 

 40. 
Which type of flip-flop is referred to as "one's catching"?
a.
J-K
c.
D
b.
toggle
d.
R-S
 

 41. 
The inputs to a J-K flip-flop are J=1 and K=1. The outputs are Q=1 and mc041-1.jpg=0. What will the outputs be after the next clock pulse occurs?
a.
Q=1, mc041-2.jpg=0
c.
Q=0, mc041-4.jpg=1
b.
Q=1, mc041-3.jpg=1
d.
Q=0, mc041-5.jpg=0
 

 42. 
The inputs to a J-K flip-flop are J=1 and K=0. The outputs are Q=1 and mc042-1.jpg=0. What will the outputs be after the next clock pulse occurs?
a.
Q=1, mc042-2.jpg=1
c.
Q=0, mc042-4.jpg=0
b.
Q=1, mc042-3.jpg=0
d.
Q=0, mc042-5.jpg=1
 



 
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