True/False
Indicate whether the
statement is true or false.
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1.
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Latches and flip-flops are used as integral parts of more complex
devices.
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2.
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Pushbutton or toggle switches are sometimes used to generate pulses for digital
circuit inputs.
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3.
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A device enabled by an edge is edge-triggered or
edge-sensitive.
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4.
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Sequential circuits are circuits whose outputs are functions only of their
present inputs.
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5.
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In a NAND latch, the gates have active-HIGH inputs and active-LOW
outputs.
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Multiple Choice
Identify the
choice that best completes the statement or answers the question.
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6.
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Elapsed time from the 50% point of the leading edge of a pulse to the 50% point
of the trailing edge is:
a. | fall time (tf) | c. | falling edge | b. | rise time
(tr) | d. | pulse width
(tw) |
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7.
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The output of a ______ is a function both of the present input conditions and
the previous conditions of the inputs and/or outputs.
a. | steering gate | c. | combinational circuit | b. | sequential circuit
| d. | gated D
latch |
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8.
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“A latch input that makes the latch store a logic 0”
describes:
a. | SET 1 | c. | NOR latch | b. | NAND latch | d. | RESET 1 |
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9.
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The difference between a latch and a flip-flop is:
a. | they are activated by opposite logic levels | b. | the present
combination of inputs | c. | the condition under which the stored bit is
allowed to change | d. | the fixed intervals during which changes
occur |
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10.
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______ can be a serious problem, particularly when a switch is used as an input
to a digital circuit that responds to individual pulses.
a. | Pulse | c. | Contact bounce | b. | Asynchronous inputs | d. | Strobing |
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11.
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A latch whose output follows its data input when its ENABLE input is
active is a:
a. | transparent latch | c. | D latch | b. | gated SR latch | d. | register |
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12.
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______ is an enabling input to a sequential circuit that is sensitive to the
positive- or negative-going edge of a waveform.
a. | A JK flip-flop | c. | Clock | b. | A strobing gate | d. | Edge |
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13.
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______ is the momentary variation of voltage from one logic level to the
opposite level and back again.
a. | Strobing | c. | Flip-flop | b. | Pulse | d. | Toggle |
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14.
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______ is the part of a signal where the logic level is in transition from a LOW
to a HIGH
a. | Rising edge | c. | Trailing edge | b. | Leading edge | d. | Falling edge |
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15.
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A circuit in an edge-triggered flip-flop that converts the active edge of a
CLOCK input to an active-level pulse at the internal latch’s SET and RESET
inputs is a(n):
a. | leading edge | c. | master reset | b. | edge detector | d. | microprocessor |
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16.
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A gated latch with a clock input is called a:
a. | momentary-contact switch | c. | programmable logic
device | b. | flip-flop | d. | data latch |
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17.
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The _____ has two inputs, SET (S) and RESET
(R).
a. | SR latch | c. | steering gate | b. | switch | d. | flip-flop |
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18.
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When a switch is operated and contact is made ______, the contact - because it
is mechanical - will bounce a few times before settling into the new position.
a. | to the master rest | c. | on a preset circuit | b. | on a new terminal | d. | on a gated
latch |
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19.
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A ______ operates only when it is held down; when released, a spring returns the
switch to its rest position.
a. | toggle | c. | set and/or reset latch | b. | PLD | d. | momentary-contact switch |
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20.
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The CLOCK input enables a circuit only while in transition, so it can be
referred to as:
a. | “dynamic” | c. | “static” | b. | level-sensitive | d. | “snapshot” |
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