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DEchapter4

True/False
Indicate whether the statement is true or false.
 

 1. 

The logical sum is the same as the “arithmetic sum.”
 

 2. 

Not every chip requires power and ground.
 

 3. 

The NOT function has one input and one output.
 

 4. 

TTL and CMOS devices differ not in their logic functions, but in their construction and electrical characteristics.
 

 5. 

For the NAND gate we can say all inputs HIGH make the output HIGH.
 

Multiple Choice
Identify the choice that best completes the statement or answers the question.
 

 6. 

How many basic logic functions are there that can be combined to make any other logic?.
a.
two
c.
six
b.
four
d.
three
 

 7. 

A gate can be categorized by examining three attributes: output, input, and ______.
a.
size
c.
shape
b.
function
d.
logical sum
 

 8. 

“Electronic device that conducts current in one direction only and illuminates when it is conducting,” describes a:
a.
digital signal
c.
light-emitting diode
b.
control switch
d.
VCC
 

 9. 

A dual in-line package (DIP) has two parallel rows of pins; the standard spacing between pins in one row is ______.
a.
0.1" (or 100 mil)
c.
0.4" (400 mil)
b.
0.3" (or 300 mil)
d.
0.6" (600 mil)
 

 10. 

A medium-scale integration is an integrated circuit having the equivalent of ______ gates in one package.
a.
12 to 100
c.
100 to 10,000
b.
100 to 1,000
d.
120 to 10,000
 

 11. 

______ is a circuit board in which connections between components are made with lines of copper on the surfaces of the circuit board.
a.
A breadboard
c.
Printed circuit board
b.
An integrated circuit
d.
Wire-wrap
 

 12. 

The only place a chip gets its required power is through the:
a.
VCC pin
c.
J-lead
b.
dual in-line package (DIP)
d.
small outline IC
 

 13. 

______ can be used as electronic switches to block or allow passage of digital waveforms.
a.
Tristate buffers
c.
SPST switches
b.
Logic gates
d.
Inverting buffers
 

 14. 

A(n) _____ gate combines all of its inputs in an AND function, then inverts the total result.
a.
OR
c.
NOT
b.
NOR
d.
NAND
 

 15. 

An _______ is shown by a bubble or an arrow symbol on the affected terminal.
a.
active HIGH
c.
active LOW
b.
inversion
d.
opposite logic level
 

 16. 

When inverting gates such as NAND and NOR are enabled, they will invert an input signal passing it to the gate output; in other words, they transmit the signal in _______.
a.
complement form
c.
small-scale integration
b.
high-impendance state
d.
large-scale integration
 

 17. 

_____ is a sophisticated technology that relies on automatic placement of chips and soldering of pins onto the surface of a circuit board, not through holes in the circuit board.
a.
TSSOP
c.
TTL
b.
QFP
d.
SMT
 

 18. 

A(n) _______, also called a NOT gate, is a logic gate that changes its input logic level to the opposite state.
a.
difference gate
c.
bubble
b.
coincidence gate
d.
inverting buffer
 

 19. 

Digital data are transferred from more than one source to one or more destinations along a common wire or _____.
a.
chip
c.
bus
b.
pin
d.
wire-wrap
 

 20. 

A _______ is list of all possible input values to a digital circuit, listed in ascending binary order, and the output response for each input combination.
a.
data book
c.
truth table
b.
datasheet
d.
Multisim file
 



 
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